This invention relates to a charge pump circuit for use in a power source circuit or the like, and more particularly to a charge pump circuit realizing high efficiency and a large current output.
In the video appliances developed in recent years such as a video camera, digital still camera (DSC), a phone with DSC, etc., CCDs (Charge Coupled Devices) for acquiring an image are used. A CCD driving circuit for driving the CCDs requires a power source circuit which providesxc2x1high voltages (ten and several V) and large currents (several mA). At present, this high voltage is created using a switching regulator.
The switching regulator can create a high voltage with high performance, i.e. high power efficiency (output power/input power). However, this circuit has a defect of generating harmonic noise in current switching, and hence must use a power source circuit as a shield. It also requires a coil as an external component.
On the other hand, the charge pump circuit can create a high voltage with small noise, but conventionally has a defect of poor power efficiency. Therefore, this charge pump circuit cannot be used as it is as a power circuit for a portable appliance which needs excellent power efficiency. If a charge pump circuit with high performance is realized, it can contribute to miniaturization of the portable appliance.
A previously known most basic charge pump circuit is a Dickson charge pump circuit. The details of this circuit are described in a technical journal xe2x80x9cJohn F. Dikson xe2x80x98On-chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Techniquexe2x80x99 IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.SC-11, NO.3 pp. 374-378 JUNE 1976.xe2x80x9d FIG. 11 is a schematic circuit diagram showing four-stage Dikson charge pump circuit. In FIG. 11, five diodes are connected in series. In FIG. 11, symbol C denotes a coupling capacitor, CL an output capacitor, and CLK and CLKB input clock pulses in opposite phases. Numeral 51 denotes a clock driver and 52 denotes a current load.
In a stable state, where a constant current Iout flows at the output, the input current supplied to the charge pump circuit includes a current coming from the input voltage Vin and current supplied from the clock driver. In disregard of a charging/discharging current to a stay capacitor, these currents are as follows. During the period of "PHgr"1=High and "PHgr"2=Low, the average current of 2 Iout flows in a direction of solid arrow. During the period of "PHgr"1=Low and "PHgr"2=High, the average current of 2 Iout flows in a direction of broken arrow. In a clock cycle, these average currents are Iout. In the stable sate, the boosted voltage Vout in the charge pump circuit can be expressed by Equation (1)
Vout=Vinxe2x88x92Vd+n(Vxcfx86xe2x80x2xe2x88x92V1xe2x88x92Vd)xe2x80x83xe2x80x83(1)
where Vxcfx86xe2x80x2 denotes a voltage amplitude which is generated by a coupling capacitor owing to a change in a clock pulse; V1 denotes a voltage drop generated by the output current Iout; Vin denotes an input voltage which is set at a power source voltage Vdd in xe2x80x9cplusxe2x80x9d voltage boosting and 0 V in xe2x80x9cminusxe2x80x9d voltage boosting; Vd denotes a forward bias diode voltage; and n denotes the number of stages of pumping. Further, V1 and Vxcfx86xe2x80x2 can be expressed by Equations (2) and (3)                     V1        =                              Iout                          f              ⁡                              (                                  C                  +                  Cs                                )                                              =                                    2              ⁢                              IoutT                /                2                                                    C              +              Cs                                                          (        2        )                                          V          ⁢                      xe2x80x83                    ⁢                      φ            xe2x80x2                          =                  V          ⁢                      xe2x80x83                    ⁢          φ          ⁢                      xe2x80x83                    ⁢                      C                          C              +              Cs                                                          (        3        )            
where C denotes a clock coupling capacitance; Cs denotes a stay capacitance at each node, Vxcfx86 denotes a clock pulse amplitude; f denotes a clock pulse frequency; and T denotes a clock period. In disregard of the charging/discharging current flowing from the clock driver into the stay capacitor and assuming that Vin=Vdd, the power efficiency of the charge pump circuit can be expressed by Equation (4)                     η        =                              VoutIout                                          (                                  n                  +                  1                                )                            ⁢              VddIout                                =                      Vout                                          (                                  n                  +                  1                                )                            ⁢              Vdd                                                          (        4        )            
In this way, the charge pump circuit performs the voltage boosting in such a manner that a charge is successively transferred to a next stage using a diode as a charge transfer device. However, from the standpoint of mounting the charge transfer device in a MOS integrated circuit, a MOS transistor can be used more easily than a pn-junction diode. For this reason, using the MOS transistor in place of the diode as the charge transfer device has been proposed. In this case, in Equation 1, Vd represents a threshold voltage Vt of a MOS transistor.
Meanwhile, in order to remove the voltage loss corresponding to the threshold voltage to realize a high performance charge pump circuit, the impedance of the charge transfer MOS transistor must be reduced according to the value of Iout. For this purpose, it is efficient to optimize the channel width of the charge transfer MOS transistor and also increase the voltage Vgs between its gate and source to exceed the power source voltage Vdd. The charge pump which has realized this is described in detail in a technical article xe2x80x9cJieh-Tsorng Wu xe2x80x98MOS Charge Pumps for Low-Voltage Operationxe2x80x99 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 33, NO. 4 APRIL 1998xe2x80x9d.
As a result of the investigation of the charge pump circuit described in the above technical article, the inventors of this invention found the following problem. A circuit diagram of a charge pump circuit described in the article is shown in FIG. 12. In FIG. 12, MD1-MD4 which are diodes for initial setting of each pump node do not contribute a pumping operation. The feature of this circuit resides in that the charge transfer MOS transistors MS1-MS3 is supplied with the gate/source voltage Vgs of 2 Vdd restored from the boosted voltage at the pumping node in the subsequent stage. However, it is difficult to supply the MOS transistor MS4 in the last stage with Vgs of 2 Vdd so that the voltage loss is inevitably generated.
Another charge pump described in the above article is a dynamic charge pump as shown in FIG. 13. In this circuit, in order to avoid reduction of Vgs of the MOS transistor MD4 to Vdd+(Vddxe2x88x92Vth) and that of the MOS transistor MDO to (Vddxe2x88x92Vth), a high-voltage clock generator in a boot-strap system is used. All the MOS transistors for MS1-MS4 are constructed of an N-channel type.
Where a current load is small, this system can be effectively used because the charge transfer MOS transistor is small in size and hence the gate stay capacitance is small. However, in order to realize the charge pump circuit which can provide a large current output, the channel width of the charge transfer MOS transistor must be as large as several milimeters (mm). As a result, the gate stay capacitance of the MOS transistor becomes large (several pF) so that it is difficult to create the clock of 2 Vdd by the boot strap system. Another technique must be proposed for applying the voltage not smaller than the power source voltage Vdd as a gate/source voltage of the charge transfer MOS transistor.
This invention has been accomplished in order to solve the above problem of the above prior art, and intends to provide a charge pump circuit which realizes high efficiency and provides a large output current. This invention also intends to assure the withstand voltage of a gate oxide film and realize optimum design of a charge transfer MOS transistor by setting the absolute value of the gate/source voltage Vgs of all the MOS transistors at 2 Vdd.
According to first aspect of the invention, a charge pump circuit comprises: (n+2) number of charge transfer MOS transistors connected in series, to an initial stage of which is supplied with a prescribed input voltage; coupling capacitors one terminals of which are connected to connecting points between the charge transfer MOS transistors, respectively; and a clock driver for supplying clock pulses opposite to each other alternately to the other terminals of the coupling capacitors, thereby producing a positive boosted voltage, wherein the charge transfer MOS transistors at rear two stages are constructed of a P-channel type and the remaining n number of charge transfer MOS transistors are constructed of an N-channel type, and gate voltage applying circuit means is provided for applying a gate voltage which makes the gate/source voltage of the charge transfer MOS transistors uniform when they turning on.
In accordance with such a means, the voltage loss due to the threshold voltage Vt of the charge transfer MOS transistor can be eliminated to provide a charge pump circuit which realize high efficiency and produce a large output current. In addition, by setting the absolute values of the gate/source voltages Vgs of all the MOS transistors at a prescribed value (e.g. 2 Vdd), the withstand voltage of the gate oxide film can be assured stably, thereby realizing an optimum design of the charge transfer MOS transistors.
According to second aspect of the invention, in a charge pump circuit, said gate voltage applying circuit means includes an inverting level shift circuit for on/off controlling said charge transfer MOS transistors of the N-channel type according to said clock pulse, and an non-inverting circuit level shift circuit for on/off controlling said charge transfer MOS transistors of the P-channel type according to said clock pulse, and as a power source on a high potential side of said inverting level shift circuit, the voltage at a connecting point of the rear stage with the boosted voltage is used, and as a power source on a low potential side of said non-inverting level shift circuit, a voltage at the connecting point of the front stage is used.
In accordance with such a means, the inverting level shift circuit and non-inverting level shift circuit can on/off controls the charge transfer MOS transistors to boost a voltage, and set the gate/source voltages Vgs of all the charge transfer MOS transistors at a prescribed value.
According to third aspect of the invention, as a power source on a high potential side of said inverting level shift circuit, a voltage at the connecting point at the stage behind one stage, while as a power source on a low potential side of a low potential side of the non-inverting level shift circuit, a voltage at the connecting point at the stage before one stage is used.
In accordance with such a means, the gate/source voltages Vgs of all the charge transfer MOS transistors can be set at 2 Vdd.
According to fourth aspect of the invention, in a charge pump circuit, a boosted voltage of the charge transfer MOS transistor at an intermediate stage is produced as a power source for other circuits.
In accordance with such a means, a power supply circuit for the other circuit which needs a high voltage can be omitted, and the integrated circuit can be designed effectively.
A fifth pump circuit is the third charge pump circuit wherein the clock supplied to said coupling capacitor and the clock pulse supplied to said inverting level shift circuit and said non-inverting level shift circuit are caused to have different duties so that current backflow through said MOS transistors is prevented.
In accordance with such a means, loss of power consumption can be prevented.